changed CFG-PM config message to use external signal (#4062)

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Jan Veeh 2024-06-12 13:43:50 +02:00 committed by GitHub
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@ -319,6 +319,7 @@ const uint8_t GPS::_message_SAVE[] = {
// As the M10 has no flash, the best we can do to preserve the config is to set it in RAM and BBR. // As the M10 has no flash, the best we can do to preserve the config is to set it in RAM and BBR.
// BBR will survive a restart, and power off for a while, but modules with small backup // BBR will survive a restart, and power off for a while, but modules with small backup
// batteries or super caps will not retain the config for a long power off time. // batteries or super caps will not retain the config for a long power off time.
// for all configurations using sleep / low power modes, V_BCKP needs to be hooked to permanent power for fast aquisition after sleep
// VALSET Commands for M10 // VALSET Commands for M10
// Please refer to the M10 Protocol Specification: // Please refer to the M10 Protocol Specification:
@ -327,40 +328,44 @@ const uint8_t GPS::_message_SAVE[] = {
// and: // and:
// https://content.u-blox.com/sites/default/files/u-blox-M10-ROM-5.10_ReleaseNotes_UBX-22001426.pdf // https://content.u-blox.com/sites/default/files/u-blox-M10-ROM-5.10_ReleaseNotes_UBX-22001426.pdf
// for interesting insights. // for interesting insights.
//
// Integration manual:
// https://content.u-blox.com/sites/default/files/documents/SAM-M10Q_IntegrationManual_UBX-22020019.pdf
// has details on low-power modes
/* /*
CFG-PM2 has been replaced by many CFG-PM commands CFG-PM2 has been replaced by many CFG-PM commands
OPERATEMODE E1 2 (0 | 1 | 2) CFG-PMS has been removed
POSUPDATEPERIOD U4 1000ms for M10 must be >= 5s try 5
ACQPERIOD U4 10 seems ok for M10 def ok CFG-PM-OPERATEMODE E1 (0 | 1 | 2) -> 1 (PSMOO), because sporadic position updates are required instead of continous tracking <10s (PSMCT)
GRIDOFFSET U4 0 seems ok for M10 def ok CFG-PM-POSUPDATEPERIOD U4 -> 0ms, no self-timed wakup because receiver power mode is controlled via "software standby mode" by legacy UBX-RXM-PMREQ request
ONTIME U2 1 will try 1 CFG-PM-ACQPERIOD U4 -> 0ms, because receiver power mode is controlled via "software standby mode" by legacy UBX-RXM-PMREQ request
MINACQTIME U1 0 will try 0 def ok CFG-PM-ONTIME U4 -> 0ms, optional I guess
MAXACQTIME U1 stick with default of 0 def ok CFG-PM-EXTINTBACKUP L -> 1, force receiver into BACKUP mode when EXTINT (should be connected to GPS_EN_PIN) pin is "low"
DONOTENTEROFF L 1 stay at 1
WAITTIMEFIX L 1 stay with 1 This is required because the receiver never enters low power mode if microcontroller is in deep-sleep.
UPDATEEPH L 1 changed to 1 for gps rework default is 1 Maybe the changing UART_RX levels trigger a wakeup but even with UBX-RXM-PMREQ[12] = 0x00 (all external wakeup sources disabled) the receivcer remains
EXTINTWAKE L 0 no ext ints in aquisition state -> potentially a bug
EXTINTBACKUP L 0 no ext ints
EXTINTINACTIVE L 0 no ext ints Workaround: Control the EXTINT pin by the GPS_EN_PIN signal
EXTINTACTIVITY U4 0 no ext ints
LIMITPEAKCURRENT L 1 stay with 1 As mentioned in the M10 operational issues down below, power save won't allow the use of BDS B1C.
*/ CFG-SIGNAL-BDS_B1C_ENA L -> 0
// CFG-PMS has been removed
// Ram layer config message: // Ram layer config message:
// b5 62 06 8a 26 00 00 01 00 00 01 00 d0 20 02 02 00 d0 40 05 00 00 00 05 00 d0 30 01 00 08 00 d0 10 01 09 00 d0 10 01 10 00 d0 // 01 01 00 00 01 00 D0 20 01 02 00 D0 40 00 00 00 00 03 00 D0 40 00 00 00 00 05 00 D0 30 00 00 0D 00 D0 10 01
// 10 01 8b de
// BBR layer config message: // BBR layer config message:
// b5 62 06 8a 26 00 00 02 00 00 01 00 d0 20 02 02 00 d0 40 05 00 00 00 05 00 d0 30 01 00 08 00 d0 10 01 09 00 d0 10 01 10 00 d0 // 01 02 00 00 01 00 D0 20 01 02 00 D0 40 00 00 00 00 03 00 D0 40 00 00 00 00 05 00 D0 30 00 00 0D 00 D0 10 01
// 10 01 8c 03 */
const uint8_t GPS::_message_VALSET_PM_RAM[] = {0x01, 0x01, 0x00, 0x00, 0x0F, 0x00, 0x31, 0x10, 0x00, 0x01, 0x00, 0xD0, 0x20,
const uint8_t GPS::_message_VALSET_PM_RAM[] = {0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0xd0, 0x20, 0x02, 0x02, 0x00, 0xd0, 0x40, 0x01, 0x02, 0x00, 0xD0, 0x40, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0xD0, 0x40,
0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0xd0, 0x30, 0x01, 0x00, 0x08, 0x00, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0xD0, 0x30, 0x00, 0x00, 0x0D, 0x00, 0xD0,
0x10, 0x01, 0x09, 0x00, 0xd0, 0x10, 0x01, 0x10, 0x00, 0xd0, 0x10, 0x01}; 0x10, 0x01};
const uint8_t GPS::_message_VALSET_PM_BBR[] = {0x00, 0x02, 0x00, 0x00, 0x01, 0x00, 0xd0, 0x20, 0x02, 0x02, 0x00, 0xd0, 0x40, const uint8_t GPS::_message_VALSET_PM_BBR[] = {0x01, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x31, 0x10, 0x00, 0x01, 0x00, 0xD0, 0x20,
0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0xd0, 0x30, 0x01, 0x00, 0x08, 0x00, 0xd0, 0x01, 0x02, 0x00, 0xD0, 0x40, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0xD0, 0x40,
0x10, 0x01, 0x09, 0x00, 0xd0, 0x10, 0x01, 0x10, 0x00, 0xd0, 0x10, 0x01}; 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0xD0, 0x30, 0x00, 0x00, 0x0D, 0x00, 0xD0,
0x10, 0x01};
/* /*
CFG-ITFM replaced by 5 valset messages which can be combined into one for RAM and one for BBR CFG-ITFM replaced by 5 valset messages which can be combined into one for RAM and one for BBR