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Disable holds / isolations on RTC IO pads after deep sleep (#3539)

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* disable holds on RTC IO pads after deep sleep

* Don't assume SOC_RTCIO_HOLD_SUPPORTED
This commit is contained in:
todd-herbert 2024-04-04 00:59:53 +13:00 committed by GitHub
parent 2caed6d29c
commit a570e50aca
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GPG Key ID: B5690EEEBB952194
2 changed files with 14 additions and 21 deletions
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23
src/graphics/EInkDisplay2.cpp
View File

@ -151,31 +151,12 @@ bool EInkDisplay::connect()
#elif defined(HELTEC_WIRELESS_PAPER_V1_0) || defined(HELTEC_WIRELESS_PAPER)
{
// Is this a normal boot, or a wake from deep sleep?
esp_sleep_wakeup_cause_t wakeReason = esp_sleep_get_wakeup_cause();
// If waking from sleep, need to reverse rtc_gpio_isolate(), called in cpuDeepSleep()
// Otherwise, SPI won't work
if (wakeReason != ESP_SLEEP_WAKEUP_UNDEFINED) {
// HSPI + other display pins
rtc_gpio_hold_dis((gpio_num_t)PIN_EINK_SCLK);
rtc_gpio_hold_dis((gpio_num_t)PIN_EINK_DC);
rtc_gpio_hold_dis((gpio_num_t)PIN_EINK_RES);
rtc_gpio_hold_dis((gpio_num_t)PIN_EINK_BUSY);
rtc_gpio_hold_dis((gpio_num_t)PIN_EINK_CS);
rtc_gpio_hold_dis((gpio_num_t)PIN_EINK_MOSI);
}
// Start HSPI
hspi = new SPIClass(HSPI);
hspi->begin(PIN_EINK_SCLK, -1, PIN_EINK_MOSI, PIN_EINK_CS); // SCLK, MISO, MOSI, SS
// Enable VExt (ACTIVE LOW)
// Unsure if called elsewhere first?
delay(100);
pinMode(Vext, OUTPUT);
digitalWrite(Vext, LOW);
delay(100);
// VExt already enabled in setup()
// RTC GPIO hold disabled in setup()
// Create GxEPD2 objects
auto lowLevel = new EINK_DISPLAY_MODEL(PIN_EINK_CS, PIN_EINK_DC, PIN_EINK_RES, PIN_EINK_BUSY, *hspi);

12
src/sleep.cpp
View File

@ -147,6 +147,18 @@ void initDeepSleep()
LOG_INFO("Booted, wake cause %d (boot count %d), reset_reason=%s\n", wakeCause, bootCount, reason);
#endif
#if SOC_RTCIO_HOLD_SUPPORTED
// If waking from sleep, release any and all RTC GPIOs
if (wakeCause != ESP_SLEEP_WAKEUP_UNDEFINED) {
LOG_DEBUG("Disabling any holds on RTC IO pads\n");
for (uint8_t i = 0; i <= 45; i++) {
if (rtc_gpio_is_valid_gpio((gpio_num_t)i))
rtc_gpio_hold_dis((gpio_num_t)i);
}
}
#endif
#endif
}